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2024年5月7日发(作者:)
EDA课程Verilog程序设计-数字时钟
module clock(clk,rst,en,madd,hadd,s,m,h);
input clk,rst,en;
input madd,hadd;
output [5:0] s,m,h;
reg [5:0] s,m,h;
always @(posedge clk)
begin
if(!rst) begin s<=0; m<=0; h<=0; end
else if(!en) begin if(!hadd) begin if(h==23) h<=0;else h<=h+1; end
else if(!madd) begin if(m==59) m<=0; else m<=m+1; end
else if(s==59) begin s<=0;
if(m==59) begin m<=0;
if(h==23) h<=0;
else h<=h+1;
end
else m<=m+1;
end
else s<=s+1;
end
else begin s<=s; m<=m; h<=h; end
end
endmodule
/*
module add1(clk,h);
input clk;
output [5:0] h;
reg [5:0] h;
always @(posedge clk)
if(h==23) h<=0; else h<=h+1;
endmodule
module add2(clk,m);
input clk;
output [5:0] m;
reg [5:0] m;
always @(posedge clk)
if(m==59) m<=0; else m<=m+1;
endmodule
/*
module count1(clk1,s1,m1,h1);
input clk1;
output [5:0] s1,m1,h1;
reg [5:0] s1,m1,h1;
always @(posedge clk1)
begin
if(s1==59) begin s1<=0;
if(m1==59) begin m1<=0;
if(h1==23) h1<=0;
else h1<=h1+1;
end
else m1<=m1+1;
end
else s1<=s1+1;
end
endmodule*/
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