按键边缘检测，控制LED亮灭

按键边缘检测，控制LED亮灭"/>

按键边缘检测，控制LED亮灭

模块代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    13:40:18 09/25/2019 
// Design Name: 
// Module Name:    touch_led_top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module touch_led_top(input 		clk,input 		rst_n,input 		touch_key,output  reg led);reg touch_key_d0;
reg touch_key_d1;
wire touch_key_flag;//边沿检测代码
assign touch_key_flag = (~touch_key_d1) & touch_key_d0;//检测上升沿
//assign touch_key_flag = touch_key_d1 & (~touch_key_d0);//检测下降沿always@(posedge clk or negedge rst_n)beginif(!rst_n)begintouch_key_d0 <= 1'b0;touch_key_d1 <= 1'b0;endelse begintouch_key_d0 <= touch_key;touch_key_d1 <= touch_key_d0;end		
end//led赋值代码
always@(posedge clk or negedge rst_n)beginif(!rst_n)led <= 1'b1;elseif(touch_key_flag)led <= ~led;elseled <= led;
endendmodule

仿真代码

`timescale 1ns / 1ps// Company: 
// Engineer:
//
// Create Date:   10:07:01 09/26/2019
// Design Name:   touch_led_top
// Module Name:   C:/Verilog/touch_led/td_touch_led.v
// Project Name:  touch_led
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: touch_led_top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// module td_touch_led;// Inputsreg clk;reg rst_n;reg touch_key;// Outputswire led;// Instantiate the Unit Under Test (UUT)touch_led_top uut (.clk(clk), .rst_n(rst_n), .touch_key(touch_key), .led(led));always #10 clk=~clk;//20nm时钟信号initial begin// Initialize Inputsclk = 0;rst_n = 0;touch_key = 0;// Wait 100 ns for global reset to finish#20;rst_n = 1;#100;touch_key = ~touch_key;#100;touch_key = ~touch_key;		#100;touch_key = ~touch_key;#100;touch_key = ~touch_key;	      // Add stimulus hereendendmodule

仿真图片