Android NDK 代码中的 SIGILL

本文介绍了Android NDK 代码中的 SIGILL的处理方法，对大家解决问题具有一定的参考价值，需要的朋友们下面随着小编来一起学习吧！

问题描述

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我在市场上有一个 NDK 应用程序，并收到了关于 SIGILL 信号的本机崩溃报告.(我使用 google breakpad 生成本机崩溃报告.)以下是详细信息:

I have an NDK app out on market and got a native crash report about a SIGILL signal. (I use google breakpad to generate native crash reports.) Here are the details:

我的应用是为 armeabi-v7a 编译的， NEON 支持.它在 NVIDIA Tegra 2 处理器上崩溃了，它是 ARM-7 (Cortex-A9).每次都会发生.(联系用户)崩溃地址在 0x399cc，信号是 SIGILL，它在我的代码中. My app is compiled for armeabi-v7a, with NEON support. It crashed on a NVIDIA Tegra 2 Processor, which is ARM-7 (Cortex-A9). It happens every time. (contacted the user) The crash address was at 0x399cc, the signal was SIGILL, and it's in my code.

注册和反汇编:

 r4 = 0x001d50f0    r5 = 0x001d50f0    r6 = 0x598e2a3c    r7 = 0x00000000
 r8 = 0x00000001    r9 = 0x001c22b0   r10 = 0x00000000    fp = 0x81216264
 sp = 0x598e2a18    lr = 0x816399cb    pc = 0x816399cc

0x000399c6 <_ZN8Analyzer15setExpAvgFactorEi+22>:    blx 0x30508
0x000399ca <_ZN8Analyzer15setExpAvgFactorEi+26>:    fconstd d16, #7
0x000399ce <_ZN8Analyzer15setExpAvgFactorEi+30>:    vldr    d17, [pc, #32]  ; 0x399f2 <_ZN8Analyzer15setExpAvgFactorEi+66>

完整的源代码和汇编程序可用这里(它很短，基本上是 2 行 C++.)

Full source and assembler available here (it's short, basically 2 lines of C++.)

您可以看到0x399cc 位于fconstd 指令的中间.根据 arm 这个指令是在 VFP-v3 中添加的，它应该(我认为)可以在任何现代处理器中使用.

You can see that 0x399cc is in the middle of the fconstd instruction. According to arm this instruction was added in VFP-v3, which should (I think) be available in any modern processor.

会发生什么?地址位于指令的中间这一事实是否指向某处损坏的指针?(请注意，回溯非常有意义，因此该函数不会以某种方式被意外调用.)还是其他什么?

What could be going on? Does the fact that the address is in the middle of an instruction point to a corrupt pointer somewhere? (Note that the backtrace makes perfect sense, so it's not like this function was somehow called on accident.) Or is it something else?

推荐答案

好的，我明白了:NVIDIA Tegra 2 只有 16 个 64 位 GPU 寄存器，因此要以它为目标，您必须使用 -mfpu 进行编译=vfpv3-d16.有问题的指令使用寄存器 d16，它太多了".:(

Ok, I got it: the NVIDIA Tegra 2 only has 16 64-bit GPU registers, and therefore to target it you must compile using -mfpu=vfpv3-d16. The instruction in question uses register d16, which is "just too many". :(

这是对员工提到此限制的 NVIDIA 论坛的参考:http://developer.nvidia/tegra/forum/optimal-performance-guidelines

Here is a reference to an NVIDIA forum where an employee mentions this limitation: http://developer.nvidia/tegra/forum/optimal-performance-guidelines

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