用Verilog HDL设计深度为128，位宽为8的FIFO

位宽为8的FIFO"/>

用Verilog HDL设计深度为128，位宽为8的FIFO

源程序
module FIFO_buffer(clk,rst,write_to_stack,read_from_stack,data_in,data_out);input clk,rst;input write_to_stack,read_from_stack;input[7:0]data_in;output[7:0]data_out;wire[7:0]data_out;wire stack_full,stack_empty;wire[2:0]addr_in,addr_out;FIFO_control u1(.stack_full(stack_full),.stack_empty(stack_empty),.clk(clk),.rst(rst),.write_to_stack(write_to_stack),.read_from_stack(read_from_stack),.write_ptr(addr_in),.read_ptr(addr_out));//FIFO的控制模块，实现读写地址信号的改变。ram_dual u2(.q(data_out),.d(data_in),.clk1(clk),.clk2(clk),.we(write_to_stack),.rd(read_from_stack),.addr_in(addr_in),.addr_out(addr_out));//根据读写地址信号，实现读与写的操作。
endmodulemodule FIFO_control(clk,rst,stack_full,stack_empty,write_to_stack,read_from_stack,write_ptr,read_ptr);parameter stack_width=8;//数据宽度为8位parameter stack_height=8;//栈有8行数据parameter stack_ptr_width=3;//由于有8位数据，因此对应有3位的地址信号，分别对应8位数据的每一位。output stack_full,stack_empty;//堆栈充满，空的两种状态output[stack_ptr_width-1:0]write_ptr,read_ptr;//3位的读/写的地址信号，input clk,rst;//时钟与复位信号input write_to_stack,read_from_stack;//进行读/写的信号reg[stack_ptr_width-1:0]write_ptr,read_ptr;reg[stack_ptr_width:0]ptr_gap;reg[stack_width-1:0]data_out;reg[stack_width-1:0]stack[stack_height-1:0];assign stack_full=(ptr_gap==stack_height);//当指针指向堆栈的最高位时，表明堆栈充满assign stack_empty=(ptr_gap==0);//当指针指向堆栈的最低位时，表明堆栈是空着的always@(posedge clk or posedge rst)beginif(rst)begindata_out<=0;read_ptr<=0;write_ptr<=0;ptr_gap<=0;//复位，写与读的地址信号全赋为0endelse if(write_to_stack&&(!stack_full)&&(!read_from_stack))beginwrite_ptr<=write_ptr+1;//当写信号为1，读信号为0且堆栈不满时,写的地址信号+1，指针+1（向堆栈最高位移动）ptr_gap<=ptr_gap+1;endelse if(!write_to_stack&&(!stack_empty)&&(read_from_stack))beginread_ptr<=read_ptr+1;//当写信号为0，读信号为1且堆栈不空时,读的地址信号+1，指针-1（向堆栈最低位移动）ptr_gap<=ptr_gap-1;endelse if(write_to_stack&&stack_empty&&read_from_stack)beginwrite_ptr<=write_ptr+1;//当写信号为1，读信号为1且堆栈空着时,写的地址信号+1，指针+1（向堆栈最高位移动）ptr_gap<=ptr_gap+1;endelse if(write_to_stack&&stack_full&&read_from_stack)beginread_ptr<=read_ptr+1;//当写信号为1，读信号为1且堆栈充满时,读的地址信号+1，指针-1（向堆栈最低位移动）ptr_gap<=ptr_gap-1;endelse if(write_to_stack&&read_from_stack&&(!stack_full)&&(!stack_empty))beginwrite_ptr<=write_ptr+1;//当写信号为1，读信号为1且堆栈既不充满也不空着时,读的地址信号+1，写的地址信号也+1read_ptr<=read_ptr+1;endend
endmodulemodule ram_dual(q,addr_in,addr_out,d,we,rd,clk1,clk2);input [7:0]d;input[2:0]addr_in,addr_out;input we,rd;input clk1,clk2;output [7:0]q;reg[7:0]q;reg[7:0]mem[7:0];//代表的是reg[7:0]mem[0];reg[7:0]mem[1]...always@(posedge clk1)beginif(we)mem[addr_in]<=d;//如果写信号生效时，此时将输入值d根据输入的地址信号赋给中间变量memendalways@(posedge clk2)begin  if(rd)q<=mem[addr_out];//如果读信号生效时，此时将中间变量mem根据输出的地址信号赋给输出值qend
endmodule测试：
`timescale 1ns/1ns
module FIFO_tb;reg clk,rst;reg[7:0]data_in;reg write_to_stack,read_from_stack;wire[7:0]data_out;FIFO_buffer u1(.clk(clk),.rst(rst),.write_to_stack(write_to_stack),.read_from_stack(read_from_stack),.data_in(data_in),.data_out(data_out));initialbeginclk=1'b0;rst=1'b1;data_in=0;write_to_stack=1; read_from_stack=0;#5 rst=0;#155 write_to_stack=0;read_from_stack=1;endalways#10 clk=~clk;initialbeginrepeat(7)#20  data_in=data_in+1;end
endmodule