ARM cortex M0+ introduction

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ARM cortex M0+ introduction

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Cortex™-M0+
Revision: r0p1
Technical Reference Manual

1、Introduction（介绍）

1.1 About the processor

The Cortex-M0+ processor is a very low gate count, highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized,low-power processor.

1.2 Features

The processor features and benefits are:

Tight integration of system peripherals reduces area and development costs.
Thumb instruction set combines high code density with 32-bit performance.
Support for single-cycle I/O access.
Power control optimization of system components.
Integrated sleep modes for low power consumption.
Fast code execution enables running the processor with a slower clock or increasing sleep mode time.
Optimized code fetching for reduced flash and ROM power consumption.
Hardware multiplier.
Deterministic, high-performance interrupt handling for time-critical applications.
Deterministic instruction cycle timing.
Support for system level debug authentication.
Serial Wire Debug reduces the number of pins required for debugging.
Support for optional instruction trace.

1.3 Interfaces

The interfaces included in the processor for external access include:

External AHB-Lite interface.
Debug Access Port (DAP).
Optional single-cycle I/O Port.

1.4 configurable options

The MULS instruction provides a 32-bit x 32-bit multiply that returns the least-significant 32-bits of the result. The processor can implement MULS in one of two ways:

As a fast single-cycle array.
As a 32-cycle iterative multiplier.

The iterative multiplier has no impact on interrupt response time because the processor abandons multiply operations to take any pending interrupt.

1.5 Design flow and architecture

TRM:Tecnical Reference Manual

1.6 Architecture & protocol information

ARM architecture
The processor implements the ARMv6-M architecture profile. See the ARMv6-M Architecture Reference Manual.

Advanced Microcontroller Bus Architecture
The system bus of the processor implements AMBA-3 AHB-Lite. See the ARM AMBA 3 AHB-Lite Protocol Specification.

Debug Access Port architecture
The Debug Access Port (DAP) is an optional component, defined by v5.1 of the ARM Debug interface specification, see the ARM Debug Interface v5 Architecture Specification.

2、Functional description

2.1 About the functions

The Cortex-M0+ processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware
debug, single-cycle I/O interfacing, and memory-protection functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processors.

Figure 2-1 shows the functional blocks of the processor.

The implemented device provides:
A low gate count processor that features:

The ARMv6-M Thumb® instruction set.
Thumb-2 technology.
Optionally, an ARMv6-M compliant 24-bit SysTick timer.
A 32-bit hardware multiplier. This can be the standard single-cycle multiplier, or a 32-cycle multiplier that has a lower area and performance implementation.
Support for either little-endian or byte invariant big-endian data accesses.
The ability to have deterministic, fixed-latency, interrupt handling.
Load/store multiple and multicycle multiply instructions that can be abandoned and restarted to facilitate rapid interrupt handling.
Optionally, Unprivileged/Privileged support for improved system integrity.
C Application Binary Interface compliant exception model.This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers.
Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature.

NVIC that features:

Up to 32 external interrupt inputs, each with four levels of priority.
Dedicated Non-Maskable Interrupt (NMI) input.
Support for both level-sensitive and pulse-sensitive interrupt lines.
Optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.
Optional relocation of the vector table

Optional debug support:

Zero to four hardware breakpoints.
Zero to two watchpoints.
Program Counter Sampling Register (PCSR) for non-intrusive code profiling, if at least one hardware data watchpoint is implemented.
Single step and vector catch capabilities.
Support for unlimited software breakpoints using BKPT instruction.
Non-intrusive access to core peripherals and zero-waitstate system slaves through a compact bus matrix. A debugger can access these devices,including memory, even when the processor is running.
Full access to core registers when the processor is halted.
Optional, low gate-count CoreSight compliant debug access through a Debug Access Port (DAP) supporting either Serial Wire or JTAG debug connections.

Bus interfaces:

Single 32-bit AMBA-3 AHB-Lite system interface that provides simple.integration to all system peripherals and memory.
Optional single 32-bit single-cycle I/O port.
Optional single 32-bit slave port that supports the DAP.

Optional Memory Protection Unit (MPU):

Eight user configurable memory regions.
Eight sub-region disables per region.
Execute never (XN) support.
Default memory map support.

3、Programmers Model

This chapter provides an overview of the application-level programmers model. It contains the following sections: omitted

3.1 instruction set summary

The processor implements the ARMv6-M Thumb instruction set, including a number of 32-bit instructions that use Thumb-2 technology. The ARMv6-M instruction set comprises:

All of the 16-bit Thumb instructions from ARMv7-M excluding CBZ, CBNZ and IT.
The 32-bit Thumb instructions BL, DMB, DSB, ISB, MRS and MSR.

Table 3-1 shows the Cortex-M0+ instructions and their cycle counts. The cycle counts are based on a system with zero wait-states.

3.1.1 arithmetic

3.1.2 logical & shift

3.1.3 Push & Pop

3.1.4 Hint

3.2 Binary compatibility with other Cortex processors

The processor implements a binary compatible subset of the instruction set and features provided by other Cortex-M profile processors. You can move software, including system level
software, from the Cortex-M0+ processor to other Cortex-M profile processors.To ensure a smooth transition, ARM recommends that code designed to operate on other Cortex-M profile processor architectures obey the following rules and configure the Configuration Control Register (CCR) appropriately:

3.3 Memory Model

The processor contains a bus matrix that arbitrates the processor core and optional Debug Access Port (DAP) memory accesses to both the external memory system and to the internal
NVIC and debug components.Priority is always given to the processor to ensure that any debug accesses are as non-intrusive as possible. For a zero wait-state system, all debug accesses to system memory, NVIC, and debug resources are completely non-intrusive for typical code execution.The system memory map is ARMv6-M architecture compliant, and is common both to the debugger and processor accesses. Transactions are routed as follows:

All accesses below 0xE0000000 or above 0xEFFFFFFF appear as AHB-Lite transactions on the AHB-Lite master port of the processor.
Accesses in the range 0xE0000000 to 0xEFFFFFFF are handled within the processor and do not appear on the AHB-Lite master port of the processor.
Data accesses to the AHB-Lite interface from both the debugger and the processor can be hardware configured to appear instead on the single-cycle I/O port.

The processor supports only word size accesses in the range 0xE0000000 - 0xEFFFFFFF. Table 3-2 shows the code, data, and device suitability for each region of the default memory map. This is the memory map used by implementations without the optional Memory Protection Unit (MPU), or when an included MPU is disabled. The attributes and permissions of all
regions, except that targeting the Cortex-M0+ NVIC and debug components, can be modified using an implemented MPU.

3.4 Processor core registers summary

Table 3-3 shows the processor core register set summary. Each of these registers is 32 bits wide.

3.5 Exceptions

NMI:Non-maskable Interrupt

4、System Control

4.1 About system control

This section describes the system control registers that control and configure various system control functions.

4.2 System control register summary

Table 4-1 gives the system control registers. Each of these registers is 32 bits wide.

4.2.1 CPUID register

5、Nested Vectored Interrupt Controller

5.1 About NVIC

External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts.Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core
are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts.
All NVIC registers are only accessible using word transfers. Any attempt to read or write a halfword or byte individually is Unpredictable.
NVIC registers are always little-endian. Processor accesses are correctly handled regardless of the endian configuration of the processor.
Processor exception handling is described in Exceptions on page 3-10.