Verilog——驱动8位led"/>
Verilog——驱动8位led
用verilog编写一个以0.5s交替循环的8个led程序
模拟驱动程序
led_testbench
`timescale 1ns/1ns
module led_tb();reg clk;reg rst;wire [7:0]LED;ledX led(.clk(clk),.rest(rst),.led(LED));//例化,记得加标签ledX led();不同的led用不同的Xinitial clk=1; //定义初始状态,0也行always #10 clk = ~clk;//每10ns翻转一次,一个周期就是20ns,模拟50MHz的晶振initial beginrst=0;#201;rst=1; //复位#4000000000;//复位结束后跑四秒钟$stop;//结束endendmodule
三种不同但结果相同的函数主体程序
- led
普通循环
`timescale 1ns / 1psmodule led(clk,rest,led);input clk;input rest;output reg [7:0]led;reg [24:0]counter;//晶振50MHz,也就是20ns。0.5s的话需要计数0.5s/20ns=25000000次//25000000需要25位二进制数,因此设定counter为[24:0]/*-----------------------------------------------------------*///计时0.5salways @(posedge clk or negedge rest)beginif(!rest)//复位要始终保持一个最高的优先级counter <= 0;else if(counter==25'd24999999)//因为从从24999999到0也需一次counter <= 0;elsecounter <= counter+1'b1;//counter自加end/*-----------------------------------------------------------*/always @(posedge clk or negedge rest)if(!rest)led <= 8'b0000_0001;else if(counter==25'd24999999)//0.5s变换一个ledbeginif(led==8'b1000_0000)led <= 8'b0000_0001;//防止到第八位后再左移变成0000_0000elseled <= led<<1;//左移一位end endmodule
- led1
使用闭环循环
`timescale 1ns / 1psmodule led(clk,rest,led);input clk;input rest;output reg [7:0]led;reg [24:0]counter;//晶振50MHz,也就是20ns。0.5s的话需要计数0.5s/20ns=25000000次//25000000需要25位二进制数,因此设定counter为[24:0]/*-----------------------------------------------------------*///计时0.5salways @(posedge clk or negedge rest)beginif(!rest)//复位要始终保持一个最高的优先级counter <= 0;else if(counter==25'd24999999)//因为从从24999999到0也需一次counter <= 0;elsecounter <= counter+1'b1;//counter自加end/*-----------------------------------------------------------*/always @(posedge clk or negedge rest)if(!rest)led <= 8'b0000_0001;else if(counter==25'd24999999)beginled <= {led[6:0],led[7]};//逻辑左移构成一个闭环,不用担心0000_0000的出现end endmodule
- led2
调用38译码器方法驱动
`timescale 1ns / 1psmodule led2(clk,rest,led);input clk;input rest;output [7:0]led;reg [24:0]counter;//晶振50MHz,也就是20ns。0.5s的话需要计数5us/20ns=25000000次//25000000需要25位二进制数,因此设定counter为[24:0]always @(posedge clk or negedge rest)beginif(!rest)//复位要始终保持一个最高的优先级counter <= 0;else if(counter==25'd24999999)//因为从从24999999到0也需一次counter <= 0;elsecounter <= counter+1'b1;//counter自加end3_8译码器///reg [2:0]counter2;always @(posedge clk or negedge rest)beginif(!rest)//复位要始终保持一个最高的优先级counter2 <= 0;else if(counter==25'd24999999)counter2 <= counter2 +1'b1;end/调用3_8译码器模块//three28 three(.a(counter2[2]),.b(counter2[1]),.c(counter2[0]),//分别将a、b、c对应counter2的2、1、0.out(led)//led是由底层模块(38译码器)驱动的。凡是由底层模块驱动的信号不管输出是reg型还是wire型,顶层都只能定义为wire型);endmodule
三八译码器程序
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Verilog——驱动8位led
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