Vivado [Place 30"/>
Vivado [Place 30
场景
- Vivado版本: 2016.4
- FPGA开发板:NEXYS 4 DDR
- 所在项目:31条单周期CPU
完整报错信息
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF] >reset_IBUF_inst (IBUF.O) is locked to IOB_X0Y82and reset_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
解决问题思路
在过去的一次课程作业中实现了分频器,在这个实验当中,没有用到板子上的晶振,也就是E3管脚,但是又有时钟信号,所以需要在XDC文件中添加:
set_property CLOCK_DEDICATED_ROUTE
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Vivado [Place 30
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