并行输入串行输出

并行输入串行输出

利用有限状态机将并行输入的数据转换为串行输出，初学veirlog，如有错误，敬请指出。

1.RTL代码

module par2ser(in,en,clk,rst,ack,out,valid);input in;
input clk;
input rst;
input en;
output out;
output valid;//when output signal is becoming valid, valid = 1
output ack;// ask for new infowire[3:0] in;
reg out;
reg[3:0] curr_state;
reg[3:0] next_state;parameter IDLE = 3'b000,BIT1 = 3'b001,BIT2 = 3'b011,BIT3 = 3'b010,BIT4 = 3'b110,FINISH = 3'b111,//finish recieving infoREADY = 3'b101;//ready for recieve infoalways@(posedge clk or negedge rst) begin if(~rst)curr_state <= IDLE;elsecurr_state <= next_state;endalways@(*) begincase(curr_state)IDLE:beginif(en)next_state = READY;elsenext_state = IDLE;endREADY:next_state = BIT1;BIT1:next_state = BIT2;BIT2:next_state = BIT3;BIT3:next_state = BIT4;BIT4:next_state = FINISH;FINISH:next_state = IDLE;default:next_state = IDLE;endcase
endalways@(posedge clk or negedge rst) beginif(~rst)out <= 0;else begincase(curr_state)BIT1:out <= in[0];BIT2:out <= in[1];BIT3:out <= in[2];BIT4:out <= in[3];default:out <= 0;endcaseend
endassign ack = (curr_state == FINISH);
assign valid = (curr_state == BIT1);endmodule

2.testbench

module par2sertb;reg clk;
reg rst;
reg en;
reg[3:0]in;
wire out;
wire ack;
wire valid;initial begin`ifdef VCD $vcdpluson;`endifrst = 0;en = 0;in = 0;#100 rst = 1;#100 en = 1;#10000 $finish;
endinitial beginclk = 0;forever #10 clk = ~clk;
endalways@(negedge ack) beginin = {$random} % 15;endpar2ser u(.clk(clk),.rst(rst),.en(en),.out(out),.in(in),.ack(ack),.valid(valid));endmodule

3.波形