问题描述
限时送ChatGPT账号..在 SystemVerilog 中声明数组和数组查询函数时,我总是感到困惑.你能详细解释一下给定的例子吗:
I am always confusing while declaring an array and Array Querying Function in SystemVerilog. Can you explain me in details for given example:
示例 1
integer matrix[7:0][0:31][15:0];
// 3-dimensional unpacked array of integers i am confuse in size
// and dimension of given array for 1 and 2 dimension its easy to
// understand but for 3 and 4-dimension its little bit confusing...
示例 2
//bit [1:5][10:16] foo [21:27][31:38];
示例 3
//module array();
bit [1:5][10:16] foo1 [21:27][31:38],foo2 [31:27][33:38];
initial
begin
$display(" dimensions of foo1 is %d foo2 is %d",$dimensions(foo1),$dimensions(foo2) );
end
输出...
dimensions of foo1 is 4 foo2 is 4
我也没有得到这个...
I am not getting this also...
推荐答案
参见 Sec: 7.4.5 Multidimensional arrays of IEEE 1800-2009
See Sec: 7.4.5 Multidimensional arrays of IEEE 1800-2009
标识符前面的维度设置打包维度.标识符后面的维度设置解包维度.
The dimensions preceding the identifier set the packed dimensions. The dimensions following the identifier set the unpacked dimensions.
bit [3:0] [7:0] joe [1:10]; // 10 elements of 4 8-bit bytes
在多维声明中,在类型之后和名称之前声明的维度(前面声明中的[3:0][7:0]
)比名称后面的维度变化更快([1:10]
在前面的声明中).引用时,压缩尺寸 ([3:0], [7:0]
) 遵循解包尺寸 ([1:10]
).
In a multidimensional declaration, the dimensions declared following the type and before the name
([3:0][7:0]
in the preceding declaration) vary more rapidly than the dimensions following the name
([1:10]
in the preceding declaration).
When referenced, the packed dimensions ([3:0], [7:0]
) follow
the unpacked dimensions ([1:10]
).
即在维度列表中,最右边的变化最快,如在 C 中.但是,打包维度的变化比未打包维度变化得更快.
i.e. In a list of dimensions, the rightmost one varies most rapidly, as in C. However, a packed dimension varies more rapidly than an unpacked one.
bit [1:10] v1 [1:5]; // 1 to 10 varies most rapidly
bit v2 [1:5] [1:10]; // 1 to 10 varies most rapidly
bit [1:5] [1:10] v3 ; // 1 to 10 varies most rapidly
bit [1:5] [1:6] v4 [1:7] [1:8]; // 1 to 6 varies most rapidly, followed by 1 to 5, then 1 to 8 and then 1 to 7
示例 1:您可以这样查看设置:
示例 2:
bit [1:5][10:16] foo [21:27][31:38];
这与示例 1 类似.
示例 3:
module array();
bit [1:5][10:16] foo1 [21:27][31:38],foo2 [31:27][33:38];
initial
begin
$display(" dimensions of foo1 is %d foo2 is %d",$dimensions(foo1),$dimensions(foo2) );
end
上述模块中的声明同
bit [1:5][10:16] foo1 [21:27][31:38];
bit [1:5][10:16] foo2 [31:27][33:38];
正如 Dave 所提到的,$dimensions
函数为您提供了打包和解包的维度总数.因为 foo1 和 foo2 都是 4 维的,所以显示的值为 4.
As Dave has mentioned, $dimensions
function gives you the total number of dimensions packed and unpacked. Sice both foo1 and foo2 are 4 dimensional the displayed value is 4.
有关此主题的更多信息,请访问以下链接.这将消除你所有的疑虑.这里提供了一个很好的表示.http://testbench.in/SV_09_ARRAYS.html
For more on this topic please go though the following link. This would clear your all doubts. A nice representation is provided here. http://testbench.in/SV_09_ARRAYS.html
这篇关于需要概念来理解系统 verilog 中的数组声明的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!
更多推荐
[db:关键词]
发布评论