问题描述
限时送ChatGPT账号..我有一个 verilog 模块的串行输出,我想使用 system-verilog 进行测试.
I have a serial output of a verilog module I'd like to testbench using system-verilog.
给定正确的串行输入SI",值为 8'h9A,名为SO"的输出将输出类似 8'hC6 的内容.
The output, called 'SO' will output something like 8'hC6 given the correct serial input 'SI' with a value of say 8'h9A.
是否有一种简单的方法来编码/解码串行 IO,而无需明确描述每个信号?
Is there an easy way to encode / decode serial IOs without having to explicitly describe each signal?
例如:
assert property @(posedge clk) $rose(EN) |-> ##[1:3] SI ##1 !SI[*2] ##1 SI[*2] ##1 !SI ##1 SI ##1 !SI
##[1:3] SO[*2] ##1 !SO[*3] ##1 SO[*2] ##1 !SO;
它看起来像一团乱麻,几乎无法阅读.我很想写
It looks like a jumbled mess and is barely readable. I'd very much like to just write
8'h9A ##[1:3] 8'hC6
但显然这行不通.任何建议或例子都非常受欢迎.提前致谢.
but obviously this doesn't work. Any advice or examples would be more than welcome. Thanks in advance.
推荐答案
尝试一个序列并参考 IEEE Std 1800-2012 第 16.10 节(局部变量):
Try a sequence and refer to IEEE Std 1800-2012 section 16.10 (Local variables):
sequence seq_serial(logic signal, local logic [7:0] expected);
byte idx = 7;
(signal == expected[idx], idx--)[*8];
endsequence : seq_serial
asrt_si0x9A_so0xC6 : assert property ( @(posedge clk)
$rose(EN) |-> ##[1:3] seq_serial(SI, 8'h9A) ##[1:3] seq_serial(SO, 8'hC6) );
这相当于提供的断言,更具可读性.
This is equivalent to the the assertion provided and is more readable.
请注意 local
关键字,它会将 expected
视为变量而不是引用,并允许您传递常量(例如 8'h9A
>, 8'hC6
) 并且仍然允许您传递网络引用.请参阅 IEEE Std 1800-2012 部分 16.8.2(局部变量形式序列声明中的参数)了解更多.
Do note the local
keyword which will treat expected
as a variable rather then a reference and allows you to pass constant (e.g. 8'h9A
, 8'hC6
) and still allows you pas net references. See IEEE Std 1800-2012 section 16.8.2 (Local variable formal arguments in sequence declarations) for more.
这是一个简单的测试平台来证明这个断言.我正在驾驶 SO
,因为我没有真正的 DUT,我想同时演示通行证和通行证.失败场景.
Here is a simple test bench to prove the assertion. I'm driving SO
because I don't have a real DUT and I want to demonstrate both a pass & fail scenario.
bit EN, clk;
logic SI,SO;
logic [7:0] si_var, so_var;
initial forever #10ns clk++; // clock generator
default clocking cb @(posedge clk); output #1ns EN,SI,SO; endclocking : cb
initial begin : test_vector
si_var = 8'h9A;
so_var = 8'hC6;
##1 cb.EN <= 1;
##($urandom_range(2,0)); // rand delay
foreach(si_var[i]) ##1 cb.SI <= si_var[i];
##($urandom_range(2,0)); // rand delay
foreach(so_var[i]) ##1 cb.SO <= so_var[i];
##1 cb.EN <= 0;
/* Now make the assertion fail */
so_var = 8'hC7; // make fail
##3 cb.EN <= 1;
##($urandom_range(2,0)); // rand delay
foreach(si_var[i]) ##1 cb.SI <= si_var[i];
##($urandom_range(2,0)); // rand delay
foreach(so_var[i]) ##1 cb.SO <= so_var[i];
##1 cb.EN <= 0;
#10ns; // little delay before finish
$finish(2);
end : test_vector
这篇关于使用 System-Verilog 进行串行测试和断言的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!
更多推荐
[db:关键词]
发布评论