Systemverilog 断言信号在仿真过程中至少出现 1 次为真

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问题描述

限时送ChatGPT账号..

我在尝试编写此断言时遇到了问题.我试图断言信号 B 必须在信号 A 为真后至少出现 1 次为真的情况.

I met a problem when trying to write this assertion. I tried to assert the scenario that signal B must be true at least 1 occurrence after signal A is true.

我写的断言如下:

example  : assert property(
       @(posedge clk) disable iff(reset)
       A |-> ##[0:$] B[->1]) else `uvm_error(....)

问题是，如果在模拟信号B在A为真后永远不会为真，则不会执行uvm_error.我期望它被执行，并且模拟报告消息:

The problem is, if during the simulation signal B is never be true after A is true, the uvm_error is not executed. I expected it to be executed, and the simulation reports the message:

example: started at xxxxxxps not finished

即使模拟结束，断言似乎也没有完成.

It seems the assertion is not finished even the simulation reaches the end.

我在google上查了一下，有一个类似的问题:断言检查 a 的切换 (0->1)信号

I looked up in google, there is a similar question: Assertion to check for the toggle (0->1) of a signal

我也试过使用 strong() 操作，它也没有帮助.

I also tried use strong() operation, it did not help as well.

如何解决这个问题?

推荐答案

不幸的是，您的解决方案取决于您使用的模拟器.我尝试了四种，每种都有不同的行为.

Unfortunately, your solution depends on which simulator you are using. I tried four and got different behaviours on each.

我认为您的解决方案是这样的:

I think your solution is this:

  example3  : assert property(
       @(posedge clk) disable iff(reset)
    A |-> s_eventually B)
    else 
      $error("%t - Assertion example3 failed", $time);

基于它在两个模拟器上工作以及我对 SVA 的理解.在一个模拟器上，action block 中的 $error 语句实际被执行，并显示消息Assertion example3 failed"；在另一个显示一般错误消息.

based on it working on two simulators and my understanding of SVA. On one simulator the $error statement in the action block actually gets executed and the message "Assertion example3 failed" is displayed; in another a generic error message is displayed.

s_ 代表强".断言意味着 B 必须在模拟结束之前的某个时间发生.

The s_ stands for "strong". The assertion means that B must occur sometime before the end of the simulation.

这是一个 MCVE.如果您包含这样的内容，您的问题会更容易回答.

Here is an MCVE. Your question would have been easier to answer had you included something like this.

module M;

  bit stop;  bit clk; initial while (!stop) #5 clk = ~clk;

  bit A, B;

  initial begin
    #20 A = 1;
    #10 A = 0;
    // #10 B = 1;
    #10 B = 0;
    #50 stop = 1;
  end

  example1  : assert property(
       @(posedge clk)
    A |-> B[->1]) 
    else 
      $error("%t - Assertion example1 failed", $time);

  example2  : assert property(
       @(posedge clk)
    A |-> eventually [0:7] B)
    else 
      $error("%t - Assertion example2 failed", $time);

  example3  : assert property(
       @(posedge clk)
    A |-> s_eventually B)
    else 
      $error("%t - Assertion example3 failed", $time);

   final
     $display("Finished!");

endmodule

https://www.edaplayground/x/2RtF

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