设计不适合ispLEVER(Design does not fit ispLEVER)

设计不适合ispLEVER(Design does not fit ispLEVER)

嗨我试图通过ispLEVER从vhdl文件创建.jed文件当我尝试创建熔丝图时出现问题，并且名为le的1位端口无法分配给引脚23（GAL22V10-15LP有24个引脚）

这是我的vhdl代码

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity alarm is port ( clk: IN std_logic; le : OUT std_logic; a: IN std_logic_vector(3 downto 0); b: IN std_logic_vector(3 downto 0); x: OUT std_logic_vector(1 downto 0)); end alarm; architecture arch_alarm of alarm is type states is (state0, state1, state2, state3 ); signal stado_pres, stado_fut: states; begin p_estados: process(stado_pres,a,b) begin case stado_pres is when state0 => x <= "00"; le <= '0'; if a = NOT(b) then stado_fut <= state1; else stado_fut <= state0; end if; when state1 => x <= "01"; if a = NOT(b) then stado_fut <= state2; else stado_fut <= state0; end if; when state2 => x <= "10"; if a = NOT(b) then stado_fut <= state3; else stado_fut <= state0; end if; when state3 => x <= "11"; if a = NOT(b) then le <= '1'; end if; stado_fut <= state0; end case; end process p_estados; p_reloj: process(clk) begin if(clk'event and clk= '1') then stado_pres <= stado_fut; end if; end process p_reloj; end arch_alarm;

并且出现的错误是：输入文件：'untitled.tt2'设备'p22v10g'注4068：由于'le'引脚23的寄存器类型无效，因此无法分配信号文件（到引脚23）。

设计不合适

FIT完成。 时间：1秒。

完成：退出代码失败：0001

编辑我已将le添加到所有状态但现在它显示另一个错误这是代码

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.std_arith.all; entity alarm is port ( clk: IN std_logic; le : OUT std_logic; a: IN std_logic_vector(3 downto 0); b: IN std_logic_vector(3 downto 0); x: OUT std_logic_vector(1 downto 0)); end alarm; architecture arch_alarm of alarm is type states is (state0, state1, state2, state3 ); signal stado_pres, stado_fut: states; begin p_estados: process(stado_pres,a,b) begin case stado_pres is when state0 => x <= "00"; le <= '0'; if a = NOT(b) then stado_fut <= state1; else stado_fut <= state0; end if; when state1 => x <= "01"; le <= '0'; if a = NOT(b) then stado_fut <= state2; else stado_fut <= state0; end if; when state2 => x <= "10"; le <= '0'; if a = NOT(b) then stado_fut <= state3; else stado_fut <= state0; end if; when state3 => x <= "11"; if a = NOT(b) then le <= '1'; end if; stado_fut <= state0; end case; end process p_estados; p_reloj: process(clk) begin if(clk'event and clk= '1') then stado_pres <= stado_fut; end if; end process p_reloj; end arch_alarm;

错误如下：注4059：信号文件无法分配（到引脚23），因为输出引脚23的条件太多。注4068：信号文件无法分配（到引脚23），因为寄存器类型为'le '23号针无效。

Hi I am trying to create a .jed file from a vhdl file through ispLEVER the problem appears when I try to create the fuse map and a port of 1 bit named le can´t be assigned to pin 23 (The GAL22V10-15LP has 24 pins)

Here is my vhdl code

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity alarm is port ( clk: IN std_logic; le : OUT std_logic; a: IN std_logic_vector(3 downto 0); b: IN std_logic_vector(3 downto 0); x: OUT std_logic_vector(1 downto 0)); end alarm; architecture arch_alarm of alarm is type states is (state0, state1, state2, state3 ); signal stado_pres, stado_fut: states; begin p_estados: process(stado_pres,a,b) begin case stado_pres is when state0 => x <= "00"; le <= '0'; if a = NOT(b) then stado_fut <= state1; else stado_fut <= state0; end if; when state1 => x <= "01"; if a = NOT(b) then stado_fut <= state2; else stado_fut <= state0; end if; when state2 => x <= "10"; if a = NOT(b) then stado_fut <= state3; else stado_fut <= state0; end if; when state3 => x <= "11"; if a = NOT(b) then le <= '1'; end if; stado_fut <= state0; end case; end process p_estados; p_reloj: process(clk) begin if(clk'event and clk= '1') then stado_pres <= stado_fut; end if; end process p_reloj; end arch_alarm;

And the error that appears is : Input file: 'untitled.tt2' Device 'p22v10g' Note 4068: Signal le cannot be assigned (to pin 23) because the register type of 'le' pin 23 is invalid.

Design does NOT fit

FIT complete. Time: 1 second.

Done: failed with exit code: 0001

EDIT I have added the le to all states but now it shows me another error Here is the code

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.std_arith.all; entity alarm is port ( clk: IN std_logic; le : OUT std_logic; a: IN std_logic_vector(3 downto 0); b: IN std_logic_vector(3 downto 0); x: OUT std_logic_vector(1 downto 0)); end alarm; architecture arch_alarm of alarm is type states is (state0, state1, state2, state3 ); signal stado_pres, stado_fut: states; begin p_estados: process(stado_pres,a,b) begin case stado_pres is when state0 => x <= "00"; le <= '0'; if a = NOT(b) then stado_fut <= state1; else stado_fut <= state0; end if; when state1 => x <= "01"; le <= '0'; if a = NOT(b) then stado_fut <= state2; else stado_fut <= state0; end if; when state2 => x <= "10"; le <= '0'; if a = NOT(b) then stado_fut <= state3; else stado_fut <= state0; end if; when state3 => x <= "11"; if a = NOT(b) then le <= '1'; end if; stado_fut <= state0; end case; end process p_estados; p_reloj: process(clk) begin if(clk'event and clk= '1') then stado_pres <= stado_fut; end if; end process p_reloj; end arch_alarm;

And the errors are : Note 4059: Signal le cannot be assigned (to pin 23) because there are too many terms for output le pin 23. Note 4068: Signal le cannot be assigned (to pin 23) because the register type of 'le' pin 23 is invalid.

最满意答案

你的信号推断了一个锁存器。 它仅分配在两个州。 全部四个分配。

输出le pin 23“的条款太多”

在这样做之后，你现在对Pin 23有太多的条款。这是因为

if a = NOT(b) then le <= '1'; end if;

“a和非b”的比较。

你可以将le移动到10个项的输出（引脚23有8个）吗？ （ stado_pres应该是两个触发器的输出，而stado_fut是触发器的输入）。

你可以用引脚将这个比较作为一个单独的信号吗？ 影响将是PAL延迟下降的两倍。

您是否获得了有关状态编码的任何指示？ （因为它们是否在x ？中重复， x是stado_pres的同义词？）

正如pwolf指出的那样

我只是分心地看着你的第二条错误信息。 le仍然倾向于基于state3缺少else赋值的锁存器。

确定与PAL相关的定时是微不足道的。 这是用来做什么的？

Your le signal infers a latch. It is assigned in only two states. Assign it in all four.

too many terms for output le pin 23"

After doing so you now have too many terms for Pin 23. It's because

if a = NOT(b) then le <= '1'; end if;

the comparison of `a and not b'.

Can you move le to an output with 10 terms (pin 23 has 8)? (stado_pres should be the output of two flip flops while stado_fut is the input to the flip flops).

Can you make this comparison a separate signal with a pin? The impact would be twice the fall through delay of the PAL.

Have you been supplied with any indication how your states are encoded? (As in are they duplicated in x?, is x a synonym for stado_pres?)

and as pwolf points out

I only looked at this distractedly for your second error message. le is still prone to a latch based on the lack of else assignment in state3.

Determining timing associated with a PAL is trivial. What is this used for?