我目前正在用VHDL设计一个32位微控制器。 我已经完成了我的指令，一切都在模拟中。 到目前为止，我已经设计了核心，ROM和RAM接口（一个单独的层，我可以根据设备接口具有潜在等待状态的任何设备）和一个带有原子寄存器的简单GPIO。 我想要集成的下一个外设是我已经设计的SPI外设。
然而我的问题是：真正的微控制器如何将其外围设备连接在一起？ 在我使用的主流微控制器（STM32，MSP430，PIC和AVR）中，它们基本上都具有“备用功能”模式，以及输入，输出和（有时）模拟。
在内部，所有外设和GPIO外设之间是否有单独的链接，例如，从SPI MISO和MOSI到某些可分配的GPIO引脚的直接链接？ 外围设备通过主系统总线与彼此进行通信似乎有点不合逻辑，因为如果您正在进行大量快速SPI传输，这将导致非常繁忙的总线！ 然而，当然每个外围设备直接相互连接是一个四十亿个逻辑单元用于多路复用器的配方吗？
谢谢！
I'm currently designing a 32bit microcontroller in VHDL. I've got my instruction set down and everything is working in simulation. As of yet, I've designed the core, the ROM and RAM interface (a seperate layer where I can interface whatever device with potential wait states depending on the device) and a simple GPIO with atomic registers. The next peripheral I want to integrate is an SPI peripheral which I've already designed.
My question however is: How do real microcontrollers link together their peripherals? Of the mainstream microcontrollers I've used (STM32, MSP430, PICs and AVRs), they all essentially have an "alternate function" mode, along with the input, output and (sometimes) analog.
Internally, are there separate links between all the peripherals and the GPIO peripheral for example, a direct link from the SPI MISO and MOSI to certain assignable GPIO pins? It seems a little illogical for peripherals to communicate with eachother over the main system bus as this would cause a very busy bus if you're doing lots of fast SPI transfers! Surely however having every peripheral directly linked to each other is a recipe for quadrillions of logic cells being used for muxes?
Thanks!
最满意答案
所以你在谈论多路复用外部引脚，首先你需要每个外设模块的地址空间gpio本身，通用I / O位敲击/采样I / O引脚的速度很慢。 spi外围设备是一个独立的外围设备，并且该块在远端具有味噌，mosi，芯片选择等。 如果你的最终实现因为大多数芯片都缺乏引脚，那么你可以在这两个外围设备之外添加一个多路复用层。 它基本上将外部引脚连接到gpio块信号或spi块信号，并且该逻辑可以具有合理的默认值。 例如，如果芯片从spi启动，那么spi功能要默认，也许主要uart（如果复用引脚上也可能需要默认）。 但除了像gpio这样的特定情况通常是默认情况。
基本上你是在谈论你的外部引脚多路复用到内部信号，以减少引脚数量。 如果你有足够的针脚，那么你不需要这样做。 在大多数情况下，隔离设计您的块，多路复用器是一个单独的块。
so you are talking about multiplexing external pins, first and foremost you want address space for each peripheral block the gpio itself, general purpose I/O bit banging/sampling I/O pins in a slow manner. the spi peripheral is a separate periperal and that block has miso, mosi, chip select, etc on the far side. now beyond that if your final implementation is pin starved as most chips are, then you add a multiplex layer beyond these two mentioned peripherals. which basically connects the external pin to either the gpio block signal or the spi block signal and that logic can have a sane default. for example if the chip boots off the spi then the spi functions want to be default, maybe the primary uart if also on multiplexed pins may want to be default. but other than specific cases like that gpio is generally the default.
basically you are talking about multiplexing your external pins to internal signals in order to reduce pin count. If you have plenty of pins then you dont need to do this. for the most part design your blocks in isolation and the multiplexer is a separate block.
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