我是Verilog的新手,并且遇到了很多麻烦。 例如,我想要有一个8个单元的数组,每个单元都是8位宽。 以下不起作用:
reg [7:0] transitionTable [0:7]; assign transitionTable[0] = 10;也没有做transitionTable[0] = 10; 或transitionTable[0] = 8'h10; 有任何想法吗?
(如果它不明显且相关:我想创建一个有限状态机,并在一个数组中指定状态转换,因为这似乎比大规模案例开关更容易。)
I'm new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following doesn't work:
reg [7:0] transitionTable [0:7]; assign transitionTable[0] = 10;neither does just doing transitionTable[0] = 10; or transitionTable[0] = 8'h10; Any ideas?
(In case it is not obvious and relevant: I want to make a finite state machine, and specify the state transitions in an array, since that seems easier than a massive case switch.)
最满意答案
当使用assign你应该将数组声明为wire而不是reg 。
When using assign you should declare the array as a wire instead of areg.
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