32位比较器波形问题（VHDL）(32-bit comparator waveform issue (VHDL))
我的波形没有变化：
我正在研究我的32位比较器项目。 我已经有一位了。 我不知道问题出在哪里。 有人可以帮我找到吗？
非常感谢
代码：1bit：
library IEEE; use IEEE.STD_LOGIC_1164.ALL; ENTITY comp1 is port (a : IN std_logic ; b : IN std_logic ; g : IN std_logic ; l : IN std_logic ; e : IN std_logic ; great : OUT std_logic ; less : OUT std_logic ; equal : OUT std_logic ); END ; ARCHITECTURE comp1_arch OF comp1 IS signal s1,s2,s3: std_logic; begin s1 <= (a and (not b)); s2 <= (not ((a and (not b)) or (b and (not a)))); s3 <= (b and (not a)); equal <= (e and s2) after 30 ns; great <= (g or(e and s1)) after 27 ns; less <= (l or(e and s3)) after 27 ns; end comp1_arch;32位：
library IEEE; use IEEE.STD_LOGIC_1164.ALL; ENTITY comp32 is GENERIC (BW : INTEGER :=32); PORT ( a_32 : IN STD_LOGIC_VECTOR (BW -1 DOWNTO 0); b_32 : IN STD_LOGIC_VECTOR (BW -1 DOWNTO 0); g_32 : OUT STD_LOGIC ; l_32 : OUT STD_LOGIC ; e_32 : OUT STD_LOGIC ); END comp32; ARCHITECTURE comp32_arch OF comp32 IS COMPONENT comp1 PORT (a,b,g,l,e : IN std_logic ; great,less,equal : OUT std_logic); END COMPONENT comp1; signal gre : std_logic_vector(BW downto 0); signal les : std_logic_vector(BW downto 0); signal equ : std_logic_vector(BW downto 0); begin gre(0)<='0';les(0)<='0';equ(0)<='0'; gen: for i in 0 to BW-1 generate biti: comp1 port map( a => a_32(i),b => b_32(i), g => gre(i), l => les(i), e =>equ(i), great => gre(i+1), less => les(i+1), equal => equ(i+1)); end generate; g_32 <= gre(BW-1); l_32 <= les(BW-1); e_32 <= equ(BW-1); end comp32_arch;试验台：
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY comp32_TB IS END comp32_TB; ARCHITECTURE behavior OF comp32_TB IS COMPONENT comp32 PORT( a_32 : IN std_logic_vector(31 downto 0); b_32 : IN std_logic_vector(31 downto 0); g_32 : OUT std_logic; l_32 : OUT std_logic; e_32 : OUT std_logic ); END COMPONENT; signal a_32 : std_logic_vector(31 downto 0) := (others => '0'); signal b_32 : std_logic_vector(31 downto 0) := (others => '0'); signal g_32 : std_logic; signal l_32 : std_logic; signal e_32 : std_logic; BEGIN uut: comp32 PORT MAP ( a_32 => a_32, b_32 => b_32, g_32 => g_32, l_32 => l_32, e_32 => e_32 ); stim_proc: process begin a_32 <="00000000000000000000000000000000";b_32<="00000000000000000000000000000000";wait for 1500 ns; a_32 <="00000000000000000000000000000001";b_32<="00000000000000000000000000000000";wait for 1500 ns; a_32 <="00000000000000000000000000000000";b_32<="10000000000000000000000000000000";wait for 1500 ns; wait; end process; END;My waveform does not change:
I am working on my 32-bit comparator project. I already have an 1 bit one. I do not know where is the issue. Anyone can help me find that?
Thanks so much
Code: 1bit:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; ENTITY comp1 is port (a : IN std_logic ; b : IN std_logic ; g : IN std_logic ; l : IN std_logic ; e : IN std_logic ; great : OUT std_logic ; less : OUT std_logic ; equal : OUT std_logic ); END ; ARCHITECTURE comp1_arch OF comp1 IS signal s1,s2,s3: std_logic; begin s1 <= (a and (not b)); s2 <= (not ((a and (not b)) or (b and (not a)))); s3 <= (b and (not a)); equal <= (e and s2) after 30 ns; great <= (g or(e and s1)) after 27 ns; less <= (l or(e and s3)) after 27 ns; end comp1_arch;32 bit:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; ENTITY comp32 is GENERIC (BW : INTEGER :=32); PORT ( a_32 : IN STD_LOGIC_VECTOR (BW -1 DOWNTO 0); b_32 : IN STD_LOGIC_VECTOR (BW -1 DOWNTO 0); g_32 : OUT STD_LOGIC ; l_32 : OUT STD_LOGIC ; e_32 : OUT STD_LOGIC ); END comp32; ARCHITECTURE comp32_arch OF comp32 IS COMPONENT comp1 PORT (a,b,g,l,e : IN std_logic ; great,less,equal : OUT std_logic); END COMPONENT comp1; signal gre : std_logic_vector(BW downto 0); signal les : std_logic_vector(BW downto 0); signal equ : std_logic_vector(BW downto 0); begin gre(0)<='0';les(0)<='0';equ(0)<='0'; gen: for i in 0 to BW-1 generate biti: comp1 port map( a => a_32(i),b => b_32(i), g => gre(i), l => les(i), e =>equ(i), great => gre(i+1), less => les(i+1), equal => equ(i+1)); end generate; g_32 <= gre(BW-1); l_32 <= les(BW-1); e_32 <= equ(BW-1); end comp32_arch;Test Bench:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY comp32_TB IS END comp32_TB; ARCHITECTURE behavior OF comp32_TB IS COMPONENT comp32 PORT( a_32 : IN std_logic_vector(31 downto 0); b_32 : IN std_logic_vector(31 downto 0); g_32 : OUT std_logic; l_32 : OUT std_logic; e_32 : OUT std_logic ); END COMPONENT; signal a_32 : std_logic_vector(31 downto 0) := (others => '0'); signal b_32 : std_logic_vector(31 downto 0) := (others => '0'); signal g_32 : std_logic; signal l_32 : std_logic; signal e_32 : std_logic; BEGIN uut: comp32 PORT MAP ( a_32 => a_32, b_32 => b_32, g_32 => g_32, l_32 => l_32, e_32 => e_32 ); stim_proc: process begin a_32 <="00000000000000000000000000000000";b_32<="00000000000000000000000000000000";wait for 1500 ns; a_32 <="00000000000000000000000000000001";b_32<="00000000000000000000000000000000";wait for 1500 ns; a_32 <="00000000000000000000000000000000";b_32<="10000000000000000000000000000000";wait for 1500 ns; wait; end process; END;最满意答案
你的链式信号向后，第一个输入要显示相等：
architecture comp32_arch of comp32 is component comp1 port (a,b,g,l,e : in std_logic ; great,less,equal : out std_logic); end component comp1; signal gre : std_logic_vector(BW downto 0); signal les : std_logic_vector(BW downto 0); signal equ : std_logic_vector(BW downto 0); begin gre(BW) <= '0'; -- gre(0) <= '0'; les(BW) <= '0'; -- les(0) <= '0'; equ(BW) <= '1'; -- equ(0) <= '0'; gen: for i in 0 to BW-1 generate biti: comp1 port map ( a => a_32(i), b => b_32(i), g => gre(i+1), -- gre(i), l => les(i+1), -- les(i), e => equ(i+1), -- equ(i), great => gre(i), -- gre(i+1), less => les(i), -- les(i+1), equal => equ(i) -- equ(i+1) ); end generate; g_32 <= gre(0); -- gre(BW);-- (BW-1); l_32 <= les(0); -- les(BW); -- (BW-1); e_32 <= equ(0); -- equ(BW); -- (BW-1); end architecture comp32_arch;这给了：
没有等于的最重要的位定义小于或大于。 如果他们都是平等的，那么一直传播。
You had your chained signals backward, and the first inputs want to show equal:
architecture comp32_arch of comp32 is component comp1 port (a,b,g,l,e : in std_logic ; great,less,equal : out std_logic); end component comp1; signal gre : std_logic_vector(BW downto 0); signal les : std_logic_vector(BW downto 0); signal equ : std_logic_vector(BW downto 0); begin gre(BW) <= '0'; -- gre(0) <= '0'; les(BW) <= '0'; -- les(0) <= '0'; equ(BW) <= '1'; -- equ(0) <= '0'; gen: for i in 0 to BW-1 generate biti: comp1 port map ( a => a_32(i), b => b_32(i), g => gre(i+1), -- gre(i), l => les(i+1), -- les(i), e => equ(i+1), -- equ(i), great => gre(i), -- gre(i+1), less => les(i), -- les(i+1), equal => equ(i) -- equ(i+1) ); end generate; g_32 <= gre(0); -- gre(BW);-- (BW-1); l_32 <= les(0); -- les(BW); -- (BW-1); e_32 <= equ(0); -- equ(BW); -- (BW-1); end architecture comp32_arch;And that gives:
The most significant bit without an equals defines either less than or greater than. If they're all equal that propagates all the way through.
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