VHDL：在一个过程中分配参数化总线(VHDL: assignment of parameterized busses in a process)

VHDL：在一个过程中分配参数化总线(VHDL: assignment of parameterized busses in a process)

作为一个学术练习，我正在设计一个具有一定限制的移位寄存器，其中之一就是我必须使用一定数量的d型触发器（其数量来自通用）。

如何使输入总线的宽度随着触发器的数量而变化？

这是原始计划（使用for循环，使用i作为递增值），但我们无法在进程内使用for循环！

else --SHIFT LEFT if (CTRL = "10") then internalInputBus (i+1) <= internalOutputBus(i); internalInputBus (0) <= SHIFT_IN; else --SHIFT RIGHT if (CTRL = "01") then internalInputBus (i) <= internalOutputBus(i+1); internalInputBus (n-1) <= SHIFT_IN; --use interesting test length thing

As an academic exercise, I am designing a shift register with certain constraints, one of which is that I have to make use of a given amount of d-type flipflops (the quantity of which comes from a generic).

How can I make the width of the input bus vary with the amount of flip flops I have?

This was the original plan (with for-loops, using i as an incrementing value), but we were not able to use a for loop inside a process!

else --SHIFT LEFT if (CTRL = "10") then internalInputBus (i+1) <= internalOutputBus(i); internalInputBus (0) <= SHIFT_IN; else --SHIFT RIGHT if (CTRL = "01") then internalInputBus (i) <= internalOutputBus(i+1); internalInputBus (n-1) <= SHIFT_IN; --use interesting test length thing

最满意答案

因为你为左移指定i+1对于右移指定i+1 i-1 ，我们可以指出你将该范围表示为小端（downto）。

'寄存器'的大小可以通过泛型分配，用于匹配端口大小和任何内部数组值大小。

signal internalInputBus: std_logic_vector (REGSIZE-1 downto 0);

在你的流程声明中，向左移动

internalInputBus <= internalInputBus(REGSIZE-2 downto 0) & right_shift_input;

在最右边的REGSIZE-1位和移位输入上使用串联运算符。

向右移动时

internalInputBus <= left_shift_input & internalInputBus(REGSIZE-1 downto 1);

我之前看到人们使用单个移位输入，但从未找到过自己有意义的应用程序。 没有内部三态信号，在某处有一个隐含的多路复用器。

循环语句是流程语句中允许的顺序语句。 我想你在结束边界时遇到了麻烦。 寻求解决方案会引导您使用串联运算符。

上面两个连接运算符示例的左右边界将引导您如何使用不遍历所有元素的循环以及另外的赋值运算符来覆盖目标数组的所有元素。

-- LEFT for i in REGSIZE-2 downto 0 loop internalInputBus(i+1) <= internalInputBus(i); end loop; internalInputBus(0) <= right_shift_input;

和

-- RIGHT for i in REGIZE-1 downto 1 loop internalInputBus(i-1) <= internalInputBus(i); end loop; internalInputBus(REGSIZE-1) <= left_shift_input;

这些只是在我的头顶完成。 买者自负。

请注意，没有插入等待的信号分配（如在循环语句中）可以读取您刚刚计划更新的值的当前值。 如果您使用的是变量目标，则需要反转顺序以防止覆盖正在评估的下一个值。 （在这种情况下，在for i in 1 to REGIZE-1 loop示例中， for i in 1 to REGIZE-1 loop ）。

Because you specify i+1 for left shift and i-1 for right shift we can adduce that you're expressing the range as little endian (downto).

The size of the 'register' can assigned via a generic, used to match the port size and any internal array value size.

signal internalInputBus: std_logic_vector (REGSIZE-1 downto 0);

In your process statement, where shifting left

internalInputBus <= internalInputBus(REGSIZE-2 downto 0) & right_shift_input;

Using the concatenation operator on the right most REGSIZE-1 bits and shift input.

When shifting right

internalInputBus <= left_shift_input & internalInputBus(REGSIZE-1 downto 1);

I've seen people use a single shift input before, but have never found an application where it makes sense myself. Without internal tristate signals there is an implied multiplexer somewhere.

Loop statements are allowed sequential statements inside a process statement. I'd imagine you were having trouble with end boundaries. Seeking a solution would lead you to an analog of using concatenation operators.

The left and right boundaries of the two concatenation operator examples above would lead you to how to use a loop not traversing all of the elements along with an additional assignment operator to cover all the elements of the target array.

-- LEFT for i in REGSIZE-2 downto 0 loop internalInputBus(i+1) <= internalInputBus(i); end loop; internalInputBus(0) <= right_shift_input;

and

-- RIGHT for i in REGIZE-1 downto 1 loop internalInputBus(i-1) <= internalInputBus(i); end loop; internalInputBus(REGSIZE-1) <= left_shift_input;

These are simply done off the top of my head. Caveat Emptor.

Note that signal assignments without intervening waits (as in a loop statement) can read the current value of a value you've just scheduled for update. If you were using a variable target instead you'd want to reverse the order to prevent overwriting the next value being evaluated. (In this case in the -- RIGHT example, for i in 1 to REGIZE-1 loop).