你如何在凿子上制造一个透明的门闩？(How do you make a transparent latch in Chisel?)

你如何在凿子上制造一个透明的门闩？(How do you make a transparent latch in Chisel?)

这是我最好的猜测，但它看起来并不像生成的行为Verilog在合成时会导致简单的透明锁存：

// DXP Latch val dxp = config(2) & config(0) val latch = Reg( lut.io.out ) val out = Mux( dxp, latch, lut.io.out )

我很欣赏你的想法。

Here is my best guess, but it doesn't look like the generated behavioral Verilog will result in a simple transparent latch when synthesized:

// DXP Latch val dxp = config(2) & config(0) val latch = Reg( lut.io.out ) val out = Mux( dxp, latch, lut.io.out )

I appreciate your ideas on this.

最满意答案

凿子不支持闩锁。 Reg()只会生成边缘触发的状态元素。

如果你真的需要锁存器，你将不得不修改凿子的后端来理解一个新的Latch()结构并生成适当的Verilog。 然而，这会让你陷入一个长长的困境，第一个是你可能会抛弃同步边缘触发的时序模型（它允许像C ++模拟器这样的工作）。

根据我们的经验，任何需要闩锁属性的关键应用程序都将由综合工具自动处理（如时间借用）。

Chisel does not support latches. Reg() will only generate edge-triggered state elements.

If you really want latches, you would have to modify the backend of Chisel to understand a new Latch() construct and generate the appropriate Verilog. However, this will take you down a long rabbit hole of difficulties, the first of which is you would probably be throwing away the synchronous, edge-triggered timing model (that allows things like the C++ emulator to work).

In our experiences, any critical applications that needed some of the properties of latches will get automatically handled by the synthesis tools (like time-borrowing).