具有多个时钟域的凿子测试器SteppedHWIOTester(chisel

试图用SteppedHWIOTester在凿子中测试asyncFifo

class AsyncFifo(width: Int, depth: Int, syncStages: Int) extends Module {
  val length = log2Ceil(depth)
  val io = IO(new Bundle {
    val clk_write = Input(Clock())
    val clk_read = Input(Clock())
    val rstn_write = Input(Bool())
    val rstn_read = Input(Bool())
    val deq = Decoupled(UInt(width.W))
    val enq = Flipped(Decoupled(UInt(width.W)))
  })
  val memory = Mem(depth, UInt(width.W))
  val reader: reader = withClock(io.clk_read)( Module(new reader(width, depth, syncStages)) )
  val writer: writer = withClock(io.clk_write)( Module(new writer(width, depth, syncStages)) )
  //some connections here...
}
class AsyncFifoHardWareTester extends SteppedHWIOTester {
  val device_under_test = Module(new AsyncFifo(32, 32, 2))
  val c = device_under_test
  enable_all_debug = true

  step(2)
  poke(c.io.enq.bits, 0x11L)
  poke(c.io.enq.valid, 0x1L)
  step(2)
  poke(c.io.enq.bits, 0x11L)
  poke(c.io.enq.valid, 0x0L)
  step(2)
  expect(c.io.deq.valid, 0x11L)
  expect(c.io.deq.bits, 0x0L)
}
 
 测试程序生成vcd，其中clk_write和clk_read由零驱动。 有没有办法在HW或PeekPoke测试仪中声明异步时钟和它们的比率？ 
Trying to test asyncFifo wrote in chisel with SteppedHWIOTester like that
 
class AsyncFifo(width: Int, depth: Int, syncStages: Int) extends Module {
  val length = log2Ceil(depth)
  val io = IO(new Bundle {
    val clk_write = Input(Clock())
    val clk_read = Input(Clock())
    val rstn_write = Input(Bool())
    val rstn_read = Input(Bool())
    val deq = Decoupled(UInt(width.W))
    val enq = Flipped(Decoupled(UInt(width.W)))
  })
  val memory = Mem(depth, UInt(width.W))
  val reader: reader = withClock(io.clk_read)( Module(new reader(width, depth, syncStages)) )
  val writer: writer = withClock(io.clk_write)( Module(new writer(width, depth, syncStages)) )
  //some connections here...
}
class AsyncFifoHardWareTester extends SteppedHWIOTester {
  val device_under_test = Module(new AsyncFifo(32, 32, 2))
  val c = device_under_test
  enable_all_debug = true

  step(2)
  poke(c.io.enq.bits, 0x11L)
  poke(c.io.enq.valid, 0x1L)
  step(2)
  poke(c.io.enq.bits, 0x11L)
  poke(c.io.enq.valid, 0x0L)
  step(2)
  expect(c.io.deq.valid, 0x11L)
  expect(c.io.deq.bits, 0x0L)
}
 
Tester generates vcd, where clk_write and clk_read are driven by zero. Is there any way to declare async clocks and theirs ratio in HW or in PeekPoke testers?
                
最满意答案
                
                    
                        
 不幸的是，目前的答案是否定的，凿子测试仪回购没有测试多个时钟的设施。 凿子团队正在努力清理和改进凿子测试人员，参见： Chisel3问题：测试人员统一看到一些激励性的讨论。 同样正在进行的是重新编写的firrtl解释器，它将明确支持多个时钟，但这可能需要几个月的时间。 
 
 人们自己做到了这一点。 您也可以在Chisel Users Group上尝试这个问题 
Unfortunately, the answer at the moment is no, the chisel-testers repo does not have the facilities for testing multiple clocks. The chisel team is working hard on a cleanup and improvement of the chisel-testers, See: Chisel3 Issues: Testers Unification to see some of the motivating discussion. Also in progress is a re-write of the firrtl interpreter that will have explicit support for multiple clocks, but that's probably a couple of months away. 
 
People have done this on their own. You might also try this question on Chisel Users Group